NXP Semiconductors /MIMXRT1052 /IOMUXC /SW_MUX_CTL_PAD_GPIO_EMC_40

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Interpret as SW_MUX_CTL_PAD_GPIO_EMC_40

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

MUX_MODE=ALT0, SION=DISABLED

Description

SW_MUX_CTL_PAD_GPIO_EMC_40 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: SEMC_RDY of instance: semc

1 (ALT1): Select mux mode: ALT1 mux port: GPT2_CAPTURE2 of instance: gpt2

2 (ALT2): Select mux mode: ALT2 mux port: LPSPI1_PCS2 of instance: lpspi1

3 (ALT3): Select mux mode: ALT3 mux port: USB_OTG2_OC of instance: usb

4 (ALT4): Select mux mode: ALT4 mux port: ENET_MDC of instance: enet

5 (ALT5): Select mux mode: ALT5 mux port: GPIO3_IO26 of instance: gpio3

6 (ALT6): Select mux mode: ALT6 mux port: USDHC2_RESET_B of instance: usdhc2

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_EMC_40

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